The present invention relates generally to integrated circuits and in particular the present invention relates to adjusting timing operations of an integrated circuit using an externally applied voltage.
Semiconductor memory devices are used in a wide variety of applications. The memory device receives data for storage, and provides stored data to external devices. Typically, the memory device is accessed through a bus by an external device, such as a microprocessor, memory controller, or application-specific integrated circuit. The bus is used to transfer address, data, and control signals between the memory device and the external circuitry accessing the memory device.
High-speed memory devices, such as static random access memories (SRAM) may operate at speeds greater than the capability of external circuitry accessing the SRAM. For example, during a read operation the SRAM may provide data earlier in time than the external circuitry is ready to receive the output data. As a result, bus contention can be experienced where data read from the SRAM is driven onto the bus while other data still resides on the bus. To avoid the undesirable consequences of two or more devices driving relatively high currents on a common bus connection for some conflicting period of time, system designers often include idle time between successive data transfer operations. By inserting idle time, the designer effectively reduces system data access speed. Alternately, system designers match speed specifications of various devices included within the system. As such a system designer may not be able to use a readily available inexpensive memory device in a system having other components which are too slow to match the speed of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which can operate at high speeds, or can be adjusted to reduce its speed such that it can be used in a system which is not adapted to take advantage of the memory device""s high speed capabilities.
The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. An integrated circuit is described which adjusts internal timing in response to an external signal.
In particular, the present invention describes an integrated circuit comprising an input connection for receiving an externally provided voltage signal, internal circuitry for providing an internal signal, and control circuitry selectively coupled to receive the externally provided voltage signal and select between a plurality of possible delay paths for internally communicating the internal signal.
In another embodiment, an integrated circuit memory device comprises an input connection for receiving an externally provided voltage signal, internal circuitry for providing an internal signal, and a delay circuit for receiving the internal signal as an input signal and providing an output signal at an output node. The delay circuit has a plurality of possible delay paths for communicating the input signal to the output node. The memory also includes control circuitry selectively coupled to receive the externally provided voltage signal and select one of the plurality of possible delay paths for the internal signal in response to the externally provided voltage signal.
In yet another embodiment, a method of operating an integrated circuit is described. The method comprises receiving an externally provided signal, selecting a first internal communication path for a control signal if the externally provided signal is in a first state, and selecting a second internal communication path for a control signal if the externally provided signal is in a second state.